The change to physical synthesis, aka SP&R, aka RTL-to-GDS-II, design tools for the 0.13-micron and 90nm process nodes is pulling several other methods and tools previously reserved for the highest ...

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...