CAMBRIDGE, UK — June 16, 2003 – ARM [(LSE: ARM); (Nasdaq: ARMHY)], the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions, today announced at Embedded Processor Forum, ...

Arm® recently announced the availability of the next version of the Arm® AMBA® 5 AXI Protocol Specification, AXI Issue K (AXI-K). This blog will explain some of the feature updates of the AMBA AXI-K ...

With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate ...

Synopsys Enhances DesignWare Ethernet IP With Support for IEEE 1588 Specification and ARM AMBA 3 AXI InterfaceSilicon-Proven IP Delivers Precision Clock ...

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from the existing AXI protocol to satisfy the cache coherency maintenance demands of SoCs with multi core processors and shared caches in ...

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.