SANTA CRUZ, Calif. — As a functional-verification consultant, Steve Burchfiel once had to construct a verification plan from hundreds of pages of continually changing specifications. Convinced that ...

The complexity of today's system-on-a-chip designs creates serious verification challenges in various respects. It's increasingly difficult to write an effective and comprehensive verification plan.

The purpose of the verification plan, or vplan as we call it, is to capture all the verification goals needed to prove that the device works as specified. It’s a big responsibility! Getting it right ...

Design verification has been the dominant portion of chip development for years, and the challenges grow bigger every day. Single dies continue to grow in transistor count and complexity. Advanced ...