在电路中，NMOS经常用作下管，S极接地，用G极来控制管子的导通截止，很方便。 NMOS用作上管时，因为S极电平不确定，即G极电平也不好确定，很不方便。 PMOS经常用作上管，S极接固定的VCC，用G极来控制管子的导通截止。 用作下管时，因为S极电源不确定，无法 ...

为特定CMOS工艺节点设计的SPICE模型可以增强集成电路晶体管的模拟。了解在哪里可以找到这些模型以及如何使用它们。 本文引用地址： 我最近写了一系列关于CMOS反相器功耗的文章。该系列中的模拟采用了LTspice库中预加载的nmos4和pmos4模型。虽然这种方法完全 ...

随着对器件的控制需求提升，越来越多的电源开关电路出现在设计中。这些设计的目的各有不同：有的需要快速开通与关断，有的需要低导通电阻+大电流，有的需要闲时0功耗。虽然应用场合不同，但做开关可是MOS的强项。 下面来介绍几种产品设计中常用的MOS做 ...

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...

For years—decades, in fact—the NMOS transistor world has been on cruise control. NMOS is naturally faster and its performance has scaled better than PMOS. PMOS has had a cost advantage. But lately, it ...

The Nature Index 2025 Research Leaders — previously known as Annual Tables — reveal the leading institutions and countries/territories in the natural and health sciences, according to their output in ...

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...

In our previous post Low Power LDO Design Techniques for Really Small Profile Applications, Part 1, we reviewed LDO design tradeoffs using an NMOS pass transistor. This design approach is proven good ...

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up.