电子工程专辑

为什么NMOS管比PMOS管更受欢迎？

在性能相当的条件下，一颗 PMOS 管的器件面积通常需要达到 NMOS 管的 2~3 倍。更大的面积不仅影响芯片的集成度，也会带来更高的导通电阻和输入输出电容，进而增加电路延迟。 与此同时，若尺寸相同，PMOS 的沟道导通电阻一般大于 NMOS，因此其开关过程中的导通 ...
电子工程专辑

为什么NMOS管比PMOS管更受欢迎？

NMOS在实际应用中为何比PMOS要更受欢迎，本文将从导电沟道、电子迁移率和器件速度等多个方面来展开讲解。 首先是在性能 ...
Semiconductor Engineering

Mobility Gets A Boost With Expanded Epi Applications

Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of ...
Electronics Weekly

X-Fab adds 375V nmos and pmos super-junction transistors to BCD chip process

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...
Nanowerk

Imec and partners study promising application of GeSn for future pMOS devices

(Nanowerk News) One promising application of GeSn would be as stressor material for Ge channels. To outperform current uniaxial compressive strained Si channel pMOSFET technology (with embedded SiGe ...
EDN

Load switches: efficient power where you need it

Load switches come in a variety of forms, including discrete MOSFETs that you can drive with your circuit's onboard logic; gate-drive ICs in combination with discrete FETs; and integrated controller, ...
EDN

IMEC Touts High-Performance Ge pMOS

Leuven, Belgium-based nanoelectronics and nanotechnology research center IMEC is detailing high-performance germanium (Ge) pMOS devices using a silicon (Si) compatible process flow at the IEEE ...
Electronics Weekly

X-Fab adds 375V nmos and pmos super-junction transistors to BCD chip process

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...
Semiconductor Engineering

Will CFETs Help The Industry Go Vertical?

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up.