Design-Reuse

Designing low-power sequential circuits using clock gating

With shrinking technologies, rapid multiplication of clock frequencies, and increasing emphasis on power reduction, low-power design is taking on a vital role. Design teams can no longer afford to ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
Design-Reuse

Averant's Solidify 6.5 Significantly Improves Combinational and Sequential Equivalency ...

Oakland, Calif. – December 12, 2017 – Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announced the release of Solidify 6.5. Some of the ...