SystemVeirlog的全面支持是开发商用仿真器的第一道门槛。市面上可以找到不少基于纯Verilog的仿真器，但是真正能完整支持SystemVerilog 的仍然屈指可数。如何全面地支持SystemVerilog语言，是开发仿真器的一个重要任务。 数字芯片的验证技术是随着Verilog语法的演变 ...

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language in a consistent way to include enhanced modeling and verification features. By adding verification ...

In an EDA Views column posted to EEdesign April 4, 2003, Mitch Weaver of Cadence Design Systems wrote of the need to extend the Verilog standard to support ever-increasing design sizes. Mr. Weaver ...